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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
Table 15: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) (Continued)
Notes 1–5 apply to all parameters and conditions
Burst C ycle Number and Burst Address Sequence
BL
16
BT
Seq
C3
0b
C2
0b
C1
0b
C0
0b
WC
Wrap
1
0
2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
A
12
B
13
C
14
D
15
E
16
F
0b
0b
0b
1b
1b
1b
1b
0b
1b
1b
0b
0b
1b
1b
1b
0b
1b
0b
1b
0b
1b
0b
0b
0b
0b
0b
0b
0b
2
4
6
8
A
C
E
3
5
7
9
B
D
F
4
6
8
A
C
E
0
5
7
9
B
D
F
1
6
8
A
C
E
0
2
7
9
B
D
F
1
3
8
A
C
E
0
2
4
9
B
D
F
1
3
5
A
C
E
0
2
4
6
B
D
F
1
3
5
7
C
E
0
2
4
6
8
D
F
1
3
5
7
9
E
0
2
4
6
8
A
F
1
3
5
7
9
B
0
2
4
6
8
A
C
1
3
5
7
9
B
D
Int
X
X
X
0b
Illegal (not supported)
Any
X
X
X
0b
No
Illegal (not supported)
wrap
Notes:
1.
2.
3.
4.
5.
C0 input is not present on CA bus. It is implied zero.
For BL = 4, the burst address represents C[1:0].
For BL = 8, the burst address represents C[2:0].
For BL = 16, the burst address represents C[3:0].
For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boun-
dary. The variable y can start at any address with C0 equal to 0, but must not start at any
address shown in the following table.
Table 16: No-Wrap Restrictions
Width
64Mb
128Mb/256Mb
512Mb/1Gb/2Gb
4Gb/8Gb
Cannot cross full-page boundary
x16
x32
FE, FF, 00, 01
7E, 7F, 00, 01
1FE, 1FF, 000, 001
FE, FF, 00, 01
3FE, 3FF, 000, 001
1FE, 1FF, 000, 001
7FE, 7FF, 000, 001
3FE, 3FF, 000, 001
Cannot cross sub-page boundary
x16
x32
7E, 7F, 80, 81
None
0FE, 0FF, 100, 101
None
1FE, 1FF, 200, 201
None
3FE, 3FF, 400, 401
None
Note:
1. No-wrap BL = 4 data orders shown are prohibited.
Table 17: MR2 Device Feature 2 (MA[7:0] = 02h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
RFU
RL and WL
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
47
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2010 Micron Technology, Inc. All rights reserved.
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